It is well known in the field of integrated circuit (IC) design and manufacture to provide protection to IC packages against electro-static discharge (ESD) events. ESD events are occurrences of high electrical potentials of limited energy that can cause damage to IC components.
FIG. 1 illustrates an example of a known centralised ESD protection circuit 110 for an IC 100, and which forms an integrated part of the IC package.
The IC 100 comprises functional circuitry 120, providing the functionality for which the IC is intended, and for which ESD protection is required. The ESD protection circuitry 110 comprises an internal ESD clamp 130, coupled to the functional circuitry 120 via isolation diodes 140. In this manner, current arising from an ESD event flows through one or more of the isolation diodes 140, into the ESD clamp 130, which absorbs the initial ESD surge to protect the functional circuitry 120 from a current spike, and then dissipates the ESD event energy safely. The isolation diodes 140 enable an electrical isolation to be provided between each pin to be protected.
Such centralised ESD protection circuitry 130, often referred to as a rail clamp, is suitable for digital applications, for example CMOS technologies. For such digital applications, ESD requirements are defined by testing standards, such as: the Jedec standard JESD 22-A11D ESD Sensitivity Testing Human Body Model (HBM); and Jedec standard JESD22_C101C Field-Induced Charged-Device Model test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components (CDM).
The purpose of HBM testing is to reproduce the EDS event that a human being could create when coming into contact with the IC. In general, the test requires the EDS protection circuitry to protect against a peak current of 2.6 Amps.
The purpose of CDM testing is to reproduce the ESD event experienced by an IC initially charged and then subsequently discharged to ground through one pin. The CDM ESD peak current is around 3 Amps.
However, for analogue applications, and in particular for analogue applications requiring a high standard of reliability, ESD protection circuitry is required to provide protection against significantly higher ESD peak currents. Examples of such applications include, by way of example, automotive systems, such as anti-lock brake systems (ABS), airbag deployment systems, electronic stabilisation program (ESP) systems, etc.
For such applications requiring a high standard of reliability, it is known for circuitry to be subjected to ESD gun testing, such as that defined in IEC6100042, ISO10605, etc. In such testing, an ESD is generated by a ‘gun’, and applied to the pins of an IC under test. The ESD gun may be charged up to 25 kVolts prior to being discharged through a resistor of 330 Ohms or 2 Kohms, depending upon the specification. Thus, the current peak can reach 90 Amps, which is significantly higher than that of HBM and CDM testing.
As will be appreciated by a skilled artisan, in order for ESD protection circuitry, for example known ESD circuitry 120 illustrated in FIG. 1, to protect against such a high current peak, the ESD clamp 130 is required to comprise a significant capacitance in order to be able to absorb the current. Furthermore, the isolation diodes would have to be able to sustain up to 90 Amps. This inherently increases the size and cost of the ESD clamp 130 and the isolation diodes 140, and thus the amount of space they take up within the IC 100, and thereby overall cost of the IC 100.
In such a case, the ESD protection circuitry may require up to around ten percent of the area of the IC. This has a direct impact on the size and the cost of the components, which in turn affects both the cost of the IC package, and the required footprint for the IC package on a printed circuit board or the like. This is particularly significant as technology advances, since the ESD protection circuitry is incapable of a reduction in size in line with that of the functional circuitry of the IC.
A further problem that has been identified with the prior art ESD protection is that, due to layout constraints of circuitry within an IC package, it is generally the case that a centralised ESD clamp may not be placed close to the isolation diodes. The resistance of metal traces connecting the isolation diodes and the ESD clamp is low, but not negligible (e.g. 0.2 Ohms to 1 Ohm), and increases with a length of the metal traces.
As will be appreciated by a skilled artisan, during an ESD gun test, the relatively high peak currents involved in the test result in significant voltage drops, across even the smallest resistances. For example, in the case of an ESD gun test comprising a 60 Amp peak current, if a metal trace is sufficiently long to comprise a resistance to 1 Ohm, the voltage drop across the metal trace will be 60 volts, which can exceed the voltage capability of the ESD protection circuitry, which may be, for example, only 45 Volts. Consequently, the length of the metal traces between the isolation diodes and the ESD clamp on the one side, and on the other side the metal traces between the ESD clamp and the ground pin, affects the ability of the ESD protection circuitry to adequately protect an IC. The resistance of a metal trace depends on its geometry aspect (length/width). It is often the case that, in order to reach a sufficiently low resistance value, the trace is required to comprise a shorter length and a greater width than can be achieved within an integrated circuit.
Alternative known methods of providing ESD protection comprise those pins to be protected being tied to power rails via diodes. In this way, a decoupling capacitor of the power supply provides some ESD protection. However, the pins must be compatible with the power supply rating (e.g. 0.6V), and the decoupling capacitor of the power supply generally is insufficient for high levels of ESD protection, such as those required in ESD gun testing.
In order to provide adequate ESD protection without incurring significant size and cost increases to an IC packages, using prior art ESD protection methods, connection pins of an IC package are required to be individually protected. In this manner, external ESD protection devices are provided individually on sensitive pins. Although this may save on the size and cost of the IC itself, the cost, both in terms of financial cost and space requirements, is simply passed on to the printed circuit board on which the IC is mounted. Indeed, as pins are protected individually, a plurality of ESD protection components are required, thereby significantly increasing the cost and required area for ESD protection.
The requirements of ESD gun testing are increasing, in particular with regard to the peak currents required to be protected against. In 2004, ESD gun testing required a 30 Amp peak current to be protected against. This increased to a peak current of 60 Amps in 2006. In 2007, the peak current required to be protected against has increased to 90 Amps. These significant increases in the required protection of ESD protection circuitry, along with the increasing demands for reduction in both size and cost of ICs, exacerbates the short comings of known ESD protection techniques.
Thus, there exists a need for improved ESD protection for integrated circuits.